Computer Science (HMC)
One means of making VLSI design tractable is to proceed from a high-level specification of a circuit in terms of functionality, to the circuit level. A notable error which may occur in a topdown design starting with a data-flow graph representation of a circuit is a design inconsistency due to deadlock. This paper attempts to further develop the theoretical basis for algorithms which analyze the deadlock property of circuits on the basis of their data-flow graph representations. A systematic scheme to verify the absence of deadlock in data-flow graphs is also presented.
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Jhon, C.S., and R.M. Keller. "Consistency testing for data-flow circuits." Proceedings for the 1984 Design Automation Conference (June 1984): 705-707. DOI: 10.1109/DAC.1984.1585889