Overview of Rediflow II Development

Document Type

Conference Proceeding


Computer Science (HMC)

Publication Date



A status report is provided on the design of Rediflow II, a proposed multiprocessor architecture based on graph reduction. We emphasize recent work on hardware design to support graph reduction, communication, and load balancing, as well as indicating an evaluation model oriented toward larger grain computation than in our previously-reported work.

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©1987 SpringerLink

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