Overview of Rediflow II Development
Computer Science (HMC)
A status report is provided on the design of Rediflow II, a proposed multiprocessor architecture based on graph reduction. We emphasize recent work on hardware design to support graph reduction, communication, and load balancing, as well as indicating an evaluation model oriented toward larger grain computation than in our previously-reported work.
Keller, RM, Slater, JW, Likes, KT. Overview of Rediflow II Development. In: Fasel JH, Keller RM, editors. Graph Reduction: Proceedings of a Workshop Santa Fé, New Mexico, USA September 29–October 1, 1986. Lect Notes Comp Sci. 1987;279: 203-214.