Overview of Rediflow II Development

Authors

Robert M. Keller, Harvey Mudd CollegeFollow
Jon W. Slater
Kevin T. Likes, University of Utah

Document Type

Conference Proceeding

Department

Computer Science (HMC)

Publication Date

1987

Abstract

A status report is provided on the design of Rediflow II, a proposed multiprocessor architecture based on graph reduction. We emphasize recent work on hardware design to support graph reduction, communication, and load balancing, as well as indicating an evaluation model oriented toward larger grain computation than in our previously-reported work.

Rights Information

©1987 SpringerLink

Terms of Use & License Information

Terms of Use for work posted in Scholarship@Claremont.

Recommended Citation

Keller, RM, Slater, JW, Likes, KT. Overview of Rediflow II Development. In: Fasel JH, Keller RM, editors. Graph Reduction: Proceedings of a Workshop Santa Fé, New Mexico, USA September 29–October 1, 1986. Lect Notes Comp Sci. 1987;279: 203-214.