Document Type

Conference Proceeding

Department

Computer Science (HMC)

Publication Date

1984

Abstract

One means of making VLSI design tractable is to proceed from a high-level specification of a circuit in terms of functionality, to the circuit level. A notable error which may occur in a topdown design starting with a data-flow graph representation of a circuit is a design inconsistency due to deadlock. This paper attempts to further develop the theoretical basis for algorithms which analyze the deadlock property of circuits on the basis of their data-flow graph representations. A systematic scheme to verify the absence of deadlock in data-flow graphs is also presented.

Comments

Previously linked to as: http://ccdl.libraries.claremont.edu/u?/irw,339.

Publisher pdf, posted with permission.

The article can also be found at http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=33447&arnumber=1585889&count=142&index=137

Rights Information

© 1984 Institute of Electrical and Electronics Engineers (IEEE). Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.

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